1. Field of the Invention
The invention relates to a method and to an apparatus for checking output signals of an integrated circuit.
2. Description of the Related Art
The operating frequencies of modern, dynamic random access memory modules (DRAMs) are becoming higher and higher. Data in specifications for initial types of memory modules define the chronological relationship which individual signals of the memory modules are to have to one another. This data in the specifications has to be guaranteed to the customers of the memory modules.
Modern test systems for measuring the time behavior of the signals of the memory modules no longer fulfill, in particular, the requirements when measuring an output time behavior of output signals of the memory modules. Inaccuracies in measurements when using the test systems are greater here than is permitted for the values stipulated in the specifications. There are various approaches to overcoming the aforesaid problem. In this context, it is attempted to use what is referred to as a “robust design” of the memory modules in order to guarantee the values of an output time behavior which can no longer be measured. In addition, it is attempted to provide novel test systems which are capable of checking whether the chronological relationships between the signals of the memory modules comply with those stipulated in the specifications.
In the case of the robust design, it is attempted to configure the output time behavior independently of process fluctuations in the manufacture of the memory modules. In this context, the significant factor will no longer be, for example, whether specific switch-on voltages of transistors or resistance values of lines of the memory modules lie in a desired tolerance range. Therefore, in terms of the design and layout, efforts are made to ensure that individual elements of the memory modules, and thus the output time behavior of selected signals, are independent of processing tolerances. However, it is disadvantageous that it is not possible to proceed as far as desired with the robust design because, in particular, it requires additional chip area, making the design expensive. Furthermore, the risk of failures occurring which cannot be tested for rises despite designs which are as robust as possible.
A problem of conventional test systems is that they are usually not capable of determining, with a high level of resolution, chronological relationships between a plurality of signals fed to the test system. This is due in particular to the fact that the test systems make available an internal time standard, generally an internal reference clock signal, with respect to which all the signals fed to the test system are measured. This means that the test system determines computationally the chronological relationships between the signals on the basis of their respective relationship with the reference clock signal. However, it is unfavorable that high chronological resolutions can only be implemented at extremely high cost in this way.
As a result, the second abovementioned approach to solving the problem has the disadvantage that modern and suitable test systems are expensive or are not at all available for high volume testing in which thousands of the memory modules have to be tested within a limited time period.